1. Field of the Invention
The invention relates to design of layouts used in fabrication of semiconductor wafers. More specifically, the invention relates to a method and an apparatus for identifying locations in a layout of an integrated circuit (IC) chip that are susceptible to fabrication issues, by matching the layout locations to a data structure (“range pattern”) containing a pattern having range(s) on dimension(s) to cover multiple patterns, which are improperly fabricated in an integrated circuit (IC) chip.
2. Related Art
In the manufacture of integrated circuit (IC) chips, minimum feature sizes have been shrinking according to Moore's law. Currently the minimum feature size is smaller than the wavelength of light used in the optical imaging system. Accordingly it has become increasingly difficult to achieve reasonable fidelity (including resolution and depth of focus) between (a) a layout as designed in a computer and (b) shapes of circuit elements formed in a wafer after fabrication (which normally involves a number of processes such as photolithography followed by Cu deposition and chemical mechanical polishing). A number of reticle enhancement technologies (RET) such as optical proximity correction (OPC), phase shifting masks (PSM), and sub-resolution assist features (SRAF) are unable to overcome such fabrication issues. For example, even after a layout (FIG. 1A and FIG. 1D) is OPC corrected (FIGS. 1B and 1E), the resulting shape in a fabricated wafer (FIGS. 1C and 1F) may have one or more defects (e.g. Wpinch falls below a minimum limit, and causes an open circuit failure in the IC chip).
Current technology (prior to the invention described below) addresses such fabrication issues by application of design rules that are typically specified by a fabrication facility (“fab”). However, use of such fab-specified design rules can result in over-specification of the design or an unnecessarily large number of defects from fabrication thereby reducing yield. The following two articles have attempted to quantify the amount of RET (e.g. in the form of OPC) that a routed layout requires and modify the routing such that the burden of mask synthesis tools is reduced: [1] L-D. Huang, M. D. F. Wong: Optical Proximity Correction (OPC)-Friendly Maze Routing, DAC 2004; and [2] J. Mitra, P. Yu, D. Pan: RADAR: RET-aware detailed routing using fast lithography simulations, DAC 2005.
In such a framework, it is typical for regions of a layout that require large amounts of RET to be tagged as hotspots. Since it is very time consuming to accurately estimate the amount of RET that a particular routed layout needs without performing the actual operation on designs (performing RET takes about 20-30 hours of simulation time for a 1-million gate design, when using a personal computer (PC) with a central processing unit (CPU) operating at 1 GHz and equipped with 1 GB memory), such methods typically use a simple aerial image simulator to find geometric shapes in the layout that are expected to print badly. Consequently, these methods lack the ability to factor in RET information when identifying potential hotspots.
Inventors of the invention described below have realized that current methods overestimate the number of hotspots due to failure to use RET information as well as failure to use details of mask synthesis (which may not be available due to intellectual property (IP) issues from use of third party designs, e.g. if hard IP cores are present in an IC design). Hence, layout geometries that can be easily corrected in a RET stage and/or mask synthesis stage typically get tagged by current methods as hotspots to be corrected during the layout routing stage. Correcting all the tagged hotspots in the layout routing stage results in overly-conservative, less than optimal routing design.